Synthesizing 3D Gaussian doping profiles, PDK Metal-1 & Euler topology...
NAND2
CMOS 2-Input NAND CADOUT = !(A · B)
A =
B =
LIVE NAND2 STATUS
Idealized static DC conduction & carrier flow model
EXPLODE & SECTION SCRUB
EXPLODE AXES
0%
1%
0%
SCRUB SECTION PLANES
OFF
OFF
OFF
LAYER
Component
STEP 1 / 8P-Substrate Wafer
CMOS 2-INPUT NAND SCHEMATIC (OUT = !(A · B))
Click any transistor, node, gate, or rail to cross-probe in 3D Layout
SARVAM BULBUL v4NAND2 Voice Tutor
Selected: None · A=OFF B=OFF → OUT=HIGH-Z
Ask me about any 3D layer, Mead-Conway λ rule, parallel PMOS pull-up, or series NMOS pull-down in this CMOS NAND2 gate.
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